Recently, the demand for nonvolatile semiconductor memory devices which are small in size and have a large capacity has dramatically increased. In particular, more attention has been paid to NAND flash memories because of its greater possibility for higher integration and capacity than those of conventional NOR flash memories.
A NAND-type flash memory includes a memory cell array in which a plurality of electrically-rewritable memory cells MTr are arranged in a matrix manner. This memory cell array has a plurality of memory cells MTr connected in series as a basic unit (NAND cell unit). This NAND cell unit is structured so that one end is connected via a selection gate transistor Tr0 to a bit line BL and the other end is connected via a selection gate transistor Tr1 to a common source line SOURCE. The bit line BL-side selection gate transistor Tr0 and the common source line SOURCE-side selection gate transistor Tr1 sandwich a plurality of memory cells MTr. Each of the memory cells MTr is connected by one word line WL to constitute a unit called a “page”. A collection of the pages constitutes a block (e.g., Japanese Patent Unexamined Publication No. 2004-192789).
In a NAND-type flash memory, data is collectively read out from and written to each page. A page is divided into a data area and a redundancy area. The data area is generally used for storing data to-be-memorized hand codes for Error Checking and Correcting (ECC). The redundancy area is used for storing a logic address and a flag data showing the right and wrong of a block page for example.
The reliability of a conventional NAND-type flash memory's flag data has been damaged due to the influence of capacitive coupling.